Why Data Center Thermal Management Can’t Wait
A panel at the upcoming ASME Summer Heat Transfer Conference examines what’s next for AI data center thermal management.
The AI infrastructure buildout is running into a thermal wall, and it is not only a software or compute problem. According to Professor Amitabh Narain of Michigan Technological University, the next phase of data center growth is being constrained by power, water, and the thermal challenge of keeping high-value AI processors alive and running at full throughput. He points to data center projects across the United States that represent hundreds of megawatts of planned capacity, while only a fraction are moving into construction. At the same time, AI multichip (GPU plus CPU) processors are reaching the 700 to 2000 W (or higher) range, with some chips carrying substantial cost and relatively short hardware refresh cycles.
When temperatures climb too high, chips throttle. That means slower time-to-tokens performance, reduced AI throughput, and lost value from hardware that cannot operate at its intended capacity. In this environment, thermal management no longer merely supports infrastructure. It has become a strategic issue for data center performance, sustainability, and return on investment.
That is the critical problem bringing researchers, engineers, and technology leaders to the American Society of Mechanical Engineers (ASME) Summer Heat Transfer Conference (SHTC) 2026 in Bellevue, Washington, later this month. Modelon’s Nithish Selvan will join the K8 Panel, Fundamentals of Data Center and Contemporary Semiconductor Thermal Management. The session brings together experts from Georgia Tech, Penn State University, UT Austin, AMD, Accelsius, Michigan Technological University, Yektasonics, and Modelon to connect fundamental research directly with industrial applications.
Modelon’s participation reflects the growing need for physics-based system simulation in data center cooling. Decisions made at the chip, rack, CDU, chiller, power, and facility levels increasingly affect one another. Understanding those multi-scale interactions early is essential to designing new cooling architectures that can keep pace with accelerating AI infrastructure demand.
Three Industries, One Connected Thermal Challenge
Ahead of the panel, we spoke with Prof. Narain, who will chair and moderate the session. His diagnosis of the core challenge was direct: the industry can no longer treat chip design, cooling hardware, and facility infrastructure as separate handoffs.
“The time has come for the three industries to come together right at the beginning. We need to look at the chip-to-cold-plate interaction, and then the cold plate to two-phase interactions for flow management from the CDU to the facilities level. If they can be integrated and harmonized, we can solve this problem.” – Prof. Amitabh Narain
The three industries he refers to are semiconductor manufacturers, cold plate and cooling hardware engineers, and data center facility operators. Each has historically evolved its own isolated design processes, safety standards, intellectual property (IP) boundaries, and performance metrics. The result is that thermal solutions are often developed after chip architecture is already fixed, while facility cooling is designed around downstream constraints rather than being co-optimized with them.
That sequential approach was workable when power densities were lower. At 700 to 2000 W per processor, and with AI inference clusters running 24/7 near peak load, the disconnect becomes much more expensive. As Prof. Narain put it: “The rate of innovation needed has to match the rate at which people are generating and consuming power.”
Cooling Must Protect Throughput, Not Just Remove Heat
One of Prof. Narain’s central points is that the industry needs to move beyond simply asking whether it can remove enough heat. For AI processors, the harder question is whether the cooling architecture can remove heat while protecting semiconductor life, eliminating hotspots, and sustaining peak throughput.
Current and emerging approaches include direct-to-chip liquid cooling, single- and two-phase cold plates, coolant distribution units (CDUs), chip-level hotspot mitigation, chillerless operation, and new forms of active two-phase cooling. Prof. Narain’s research group is specifically exploring active methods that reorganize fluid boiling behavior directly near the chip surface. In controlled research settings, he described sustained reductions in chip temperature of around 20 degrees Celsius—a result that illustrates why a closer integration between chip, cold plate, and system design is so valuable.
The SHTC panel will examine these technologies from both a fundamental and a practical perspective. The goal is not only to compare competing cooling methods, but to understand how they dynamically interact with real data center constraints: energy availability, water use, hardware refresh cycles, time-to-tokens performance, and facility-level thermal design.
Waste Heat is an Opportunity, Not Just a Problem
One of the less-discussed dimensions of the data center thermal challenge is what happens to the heat after it is removed. Current liquid cooling systems often reject heat as relatively low-temperature warm water, limiting the opportunity for useful thermodynamic recovery. But as power densities rise and cooling architectures evolve, waste heat can become a highly valuable system resource.
Prof. Narain described a research direction in which higher-value, high-exergy heat streams can support clean electricity generation and district heating. “We can generate 20 to 25 megawatts of electricity and still have 50 degrees Celsius warm water available for district heating for every 200-plus MWe data center.”
He emphasized that the right industry partners are now needed to evaluate, validate, and scale these thermodynamic concepts in commercial deployments.
This is exactly the type of system-level question the K8 panel is designed to address. The panel’s scope includes data center and building thermal management, chillerless operation, waste heat utilization, and the potential for clean electricity generation through direct waste heat recovery. These are no longer isolated cooling choices; they are structural, architectural choices that dictate the economics and sustainability of the entire data center ecosystem.
Where System Simulation Fits
For engineers working on data center cooling today, the potential design space is enormous. A cooling loop must seamlessly couple chip thermal loads, cold plate geometries, coolant properties, CDU performance, chiller capacities, facility controls, power infrastructure, and dynamic workload behavior. These variables interact dynamically as AI workloads shift rapidly between training and inference, causing thermal loads to vary across racks and systems.
Physical testing remains essential, but it cannot explore this expansive design space quickly or cheaply enough on its own. By the time a full hardware configuration is built for physical testing, many critical architectural decisions have already been locked in.
This is where system-level simulation becomes critical. At Modelon, we build physics-first simulation models using Modelica and the open FMI standard. These models help engineering teams accurately represent the complete cooling chain—from rack-level heat loads through CDUs, chillers, and facility plants—before final hardware decisions are frozen. The value is not in replacing testing, but in compressing the design iteration cycle, exposing coupled-system behavior earlier, and helping teams effectively weigh design tradeoffs across the full architecture.
That aligns perfectly with the core argument Prof. Narain is making about co-design. The physical layers must be analyzed as a single, connected system, not handled as sequential handoffs. Simulation makes that visibility possible early in the process, when design decisions are still open and interdisciplinary collaboration can have the greatest impact.
Join the Conversation in Bellevue
The K8 Panel on Fundamentals of Data Center and Contemporary Semiconductor Thermal Management takes place on Monday, July 27, in Bellevue, Washington, as part of ASME SHTC 2026.
The comprehensive session will cover:
- High-power XPU thermal management & chip-level hotspot mitigation
- Direct-to-chip liquid cooling architectures
- Data center and building thermal management integrations
- Time-to-tokens throughput optimizations & hardware refresh cycles
- Chillerless operation & macro-scale waste heat utilization
If you are attending SHTC 2026, we hope to see you there. A post-event summary of the panel discussion will be shared right here on the Modelon blog following the conference to continue this vital conversation.
Reference: Amitabh Narain, Hardik Bhutka, Ranjeeth Naik, Nirgun Mohite, and Yagel Belikoff, “Piezo-Actuated Enhanced Nucleate Boiling: From Saturated to Controlled Flash Regimes in Two-Phase Direct-to-Chip Cooling for AI Superchips and Data Centers,” ASME Journal of Heat and Mass Transfer. DOI
